The phase-locked loop is one of the fundamental parts in nearly all modern radio apparatus. FIG. 1 shows a high-frequency frequency synthesizer which produces an oscillating signal at a desired frequency such that the phase of the signal is in known relation to the phase of a certain reference signal. A programmable digital divider 101 has two input signals one of which is generated, in a manner described later on, from an oscillating output signal produced by the circuit and the other is a reference signal REF. In the divider 101 the input signals are divided by pre-programmed divisors. The resulting lower-frequency signals are taken to a phase comparator 102 which has two outputs UP and DOWN. The phase comparator 102 usually produces one output pulse per each input signal cycle. If the phase of the signal brought to the first input of the phase comparator 102 lags with respect to the phase of the signal brought to the second input, the phase comparator generates an UP output pulse and, correspondingly, if the phase of the signal brought to the first input leads with respect to the phase of the signal brought to the second input, the phase comparator generates a DOWN output pulse. These pulses control a charge pump 103 the output of which is connected to a loop filter 104. The operation of the charge pump 103 depends on the control pulses brought to it such that in response to an UP pulse the charge pump sources electric current to the loop filter and in response to a DOWN pulse it sinks electric current from the loop filter. The amount of electric charge sourced or sunk by the charge pump is in proportion to the width of the control pulse brought to it.
It is the task of the loop filter 104 to smooth the fluctuations caused by the alternately increasing and decreasing electric charge into a direct-voltage signal by means of which it controls a voltage-controlled oscillator (VCO) 105. The greater the charge pumped by the charge pump 103 to the loop filter 104, the higher the voltage used to control the oscillator and the higher the frequency of the oscillating signal generated by the oscillator. Similarly, sinking of current to the charge pump 103 as a result of a DOWN pulse decreases the voltage level of the DC control signal produced by the loop filter 104 and thus decreases the frequency of the oscillating signal generated by the oscillator 105. The oscillating signal is the output signal of the circuit. It is also taken to a predivider 106 which produces the first input signal to the programmable digital divider 101. The predivider 106 scales the output signal to a suitable frequency range so that it can be further divided in the programmable digital divider 101 in such a manner that the frequency of the output signal produced can be selected.
A usual disadvantage of the circuit depicted in FIG. 1 is its limited sensitivity to rely small phase differences. Assuming that the input signals brought to the phase comparator 102 differ from each other only a little, the phase comparator should (generate an UP or DOWN pulse the length of which would ideally be near zero. However, it is difficult to produce very short control pulses, so in practice there is around the exact correct phase a so-called dead zone, i.e. a zone of small phase errors where the phase comparator produces no control pulse to the charge pump and, hence, the control signal of the voltage-controlled oscillator is not changed. The dead zone causes that the frequency and phase of the output signal of the circuit may vary randomly within the dead zone, which is functionally disadvantageous.
From U.S. Pat. No. 4,322,643 (to Preslar) it is known a phase comparator according to FIG. 2, which partly eliminates the problem of the dead zone. The idea is to use an internal delay line 201 in the phase comparator so that both the UP and DOWN pulses have a certain minimum length. So, the phase comparator generates both an UP and DOWN pulse per each input signal cycle. If the phase of the first input signal lags with respect to the phase of the second input signal, the phase comparator produces a minimum-length DOWN pulse and an UP pulse the length of which equals the minimum length plus an amount proportional to the phase difference. Similarly, if the phase of the first input signal leads the phase of the second input signal, the phase comparator produces a minimum-length UP pulse and a DOWN pulse the length of which equals the minimum length plus an amount proportional to the phase difference. Both the UP and DOWN output pulses control charge pumps 202 and 203 of their own. The charge pump signals are combined before being taken to an integrator 204 which in practice is the same as the loop filter 104 shown in FIG. 1. So, part of the current produced by one charge pump is always directed to the other charge pump and only the current "left over" is directed to the integrator.
FIG. 3 illustrates the relationship between input signal phase difference and output pulses. Curve 301 represents a first input signal, curve 302 a second input signal. curve 303 the UP output pulses and curve 304 represents the DOWN output pulses. Curves 301 and 302 show that initially the phase of the first input signal lag,s with respect to the phase of the second input signal, then for one cycle the phase difference is zero and then the phase of the first input signal leads with respect to the phase of the second input signal. Curves 303 and 304 show that before the turn-around of the phase difference the length of the UP output pulses exceeds the minimum length and, correspondingly, after the turnaround of the phase difference the length of the DOWN output pulses exceeds the minimum length. Note that in Preslar's arrangement the output pulse polarity is reverse, i.e. a pulse means a momentary shift from logic 1 to logic 0. It is characteristic of the operation of Preslar's arrangement that the output pulses start at different times but always end simultaneously.
In practice, the arrangement according to FIGS. 2 and 3 has not been found optimal.